1. Field of the Invention
The invention relates to a method for fabricating strained-silicon CMOS transistors.
2. Description of the Prior Art
The performance of MOS transistors has increased year after year with the diminution of critical dimensions and the advance of large-scale integrated circuits (LSI). However, it has been recently pointed out that the miniaturization attained by a lithographic technology has reached its limit. Therefore, how to improve the carrier mobility so as to increase the speed performance of MOS transistors has become a major topic for study in the semiconductor field. For the known arts, attempts have been made to use a strained silicon layer, which has been grown epitaxially on a silicon substrate with a silicon germanium (SiGe) layer disposed therebetween. In this type of MOS transistor, a biaxial tensile strain occurs in the epitaxy silicon layer due to the silicon germanium which has a larger lattice constant than silicon, and, as a result, the band structure alters, and the carrier mobility increases. This enhances the speed performance of the MOS transistors.
Please refer to FIGS. 1-4. FIGS. 1-4 are perspective diagrams illustrating a method for fabricating a strained-silicon CMOS transistor according to the prior art. As shown in FIG. 1, a semiconductor substrate 100 having an NMOS region 102 and a PMOS region 104 is provided, in which the NMOS region 102 and the PMOS region 104 are separated by a shallow trench isolation 106. Each of the NMOS region 102 and the PMOS region 104 includes a gate structure. The NMOS gate structure includes an NMOS gate 108 and a gate dielectric 114 disposed between the NMOS gate 108 and the semiconductor substrate 100. The PMOS gate structure includes a PMOS gate 110 and a gate dielectric 114 disposed between the PMOS gate 110 and the semiconductor substrate 100. The sidewall of the NMOS gate 108 and the PMOS gate 110 includes an offset spacer 112 composed of silicon oxide or silicon nitride.
Next, an ion implantation process is performed to form a lightly doped drain 118 and 119 in the semiconductor substrate 100 surrounding the NMOS gate 108 and the PMOS gate 110, and a spacer 113 is form on the sidewall of the NMOS gate 108 and the PMOS gate 110 thereafter. Next, another ion implantation process is performed to form a source/drain region 116 around the NMOS gate 108 and a source/drain region 117 around the PMOS gate 110 within the semiconductor substrate 100. A rapid thermal annealing process is performed thereafter to use a temperature between 900° C. to 1050° C. to activate the dopants within the source/drain region 116 and 117 and repair the lattice structure of the semiconductor substrate 100 which has been damaged during the ion implantation process. An NMOS transistor 132 and a PMOS transistor 134 are thus formed in the NMOS region 102 and the PMOS region 104 respectively.
As shown in FIG. 2, an etching process is performed by using the gate structures of the NMOS region 102 and the PMOS region 104 as a mask to form a recess 120 in the corresponding semiconductor substrate 100 not covered by the NMOS gate 108 and the PMOS gate 110. After the recess 120 is formed, as shown in FIG. 3, a selective epitaxial growth process is conducted to form an epitaxial layer 122 in the recess 120 of the NMOS region 102 and the PMOS region 104. The epitaxial layer 122 is preferably composed of silicon germanium.
Next, as shown in FIG. 4, a metal layer (not shown) composed of nickel is disposed on the NMOS transistor 132 and the PMOS transistor 134, and a rapid thermal annealing process is performed to react the metal layer with the NMOS gate 108, the PMOS gate 110, and the source/drain region 116 and 117 to form a plurality of salicide layers 115.
In light of the above, the conventional method for fabricating a strained-silicon CMOS transistor usually forms a spacer on the sidewall of the gate, and deposits an epitaxial layer in the semiconductor substrate with respect to the source/drain region of the NMOS region and the PMOS region. This approach allows the silicon germanium contained in the epitaxial layer to facilitate the carrier mobility of the transistor. However, due to the position of the spacer, the effect of silicon germanium imposed on the channel region is degraded, thereby limiting the performance of the CMOS transistor.